Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Ficha De Dados

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Programmer’s Model 
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
2-19
The FSR accessed is determined by the value of the Opcode_2 field:
Opcode_2 = 0 
Data Fault Status Register (DFSR).
Opcode_2 = 1 
Instruction Fault Status Register (IFSR).
The fault type encoding is listed in Table 3-9 on page 3-22.
You can access the FSRs using the following instructions:
MRC p15, 0, <Rd>, c5, c0, 0 ;read DFSR
MCR p15, 0, <Rd>, c5, c0, 0 ;write DFSR
MRC p15, 0, <Rd>, c5, c0, 1 ;read IFSR
MCR p15, 0, <Rd>, c5, c0, 1 ;write IFSR
The format of the Fault Status Register is shown in Figure 2-8.
Figure 2-8 FSR format
Table 2-15 shows the bit field descriptions for the FSR. 
UNP/SBZ
31
9 8 7
4 3
0
0
Domain
Status
Table 2-15 FSR bit field descriptions
Bits
Description
[31:9] UNP/SBZP.
[8] 
Always reads as zero. Writes ignored.
[7:4] 
Specifies which of the 16 domains (D15-D0) was being 
accessed when a data fault occurred.
[3:0]
Type of fault generated (see Table 2-16 on page 2-20).