Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Ficha De Dados

167

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Clock Generator User Interface is embedded within the Power Management Controller and is described in 

. However, the Clock Generator registers are named

CKGR_.

The Clock Generator is made up of:



One Low Power 32768 Hz Slow Clock Oscillator with bypass mode



One Low-Power 32 kHz RC oscillator



One Low-Power 12 MHz RC oscillator



One 16 MHz Main Oscillator, which can be bypassed.



One 400 to 800 MHz programmable PLLA, capable to provide the clock MCK to the processor, and to the 
peripherals. This PLL has an input divider to offer a wider range of output frequencies from the 16 MHz input, the 
only limitation being the lowest input frequency shall be higher or equal to 2 MHz.



One 100 MHz programmable PLLB dedicated to USB Full Speed operations. This PLL has an input divider to offer 
a wider range of output frequencies from the 16 MHz input, the only limitation being the lowest input frequency 
shall be higher or equal to 2 MHz.