Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Ficha De Dados
Códigos do produto
AT91SAM9N12-EK
421
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices, in particular
CAS latency, burst length and to disable DLL reset. The application must set Mode to 3 in the Mode Register (see
) and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9
columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000
columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000
) to high (OCD calibration
default).
16. An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. The application must set Mode to
5 in the Mode Register (see
) and perform a write access to the DDR2-SDRAM to
acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For
example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM
write access should be done at the address 0x20400000.
example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM
write access should be done at the address 0x20400000.
17. Program OCD field into the Configuration Register (see
) to low (OCD calibration mode
exit).
18. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The application must set Mode to 5
in the Mode Register (see
) and perform a write access to the DDR2-SDRAM to
acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For
example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM
write access should be done at the address 0x20400000.
example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM
write access should be done at the address 0x20400000.
19. A mode Normal command is provided. Program the Normal mode into Mode Register (see
20. Perform a write access to any DDR2-SDRAM address.
21. Write the refresh rate into the count field in the Refresh Timer register (see
between refresh cycles). The DDR2-SDRAM device requires a refresh every 15.625 µs or 7.81 µs. With a 133
MHz frequency, the refresh timer count register must to be set with (15.625*133 MHz) = 2079 i.e. 0x081f or
(7.81*133 MHz) = 1039 i.e. 0x040f.
MHz frequency, the refresh timer count register must to be set with (15.625*133 MHz) = 2079 i.e. 0x081f or
(7.81*133 MHz) = 1039 i.e. 0x040f.
After initialization, the DDR2-SDRAM devices are fully functional.