Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Ficha De Dados
Códigos do produto
AT91SAM9N12-EK
426
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 31-8. Write Command Followed By a Read Command without Burst Write Interrupt, Low-power DDR1-SDRAM Device
In the case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle
prior to the read command to avoid writing invalid data. See
prior to the read command to avoid writing invalid data. See
Figure 31-9. Single Write Access Followed By A Read Access Low-power DDR1-SDRAM Devices
Twrd = BL/2 +2 = 8/2 +2 = 6
Twr = 1
SDCLK
col a
col a
A[12:0]
NOP
WRITE
NOP
READ
BST
NOP
COMMAND
0
BA[1:0]
DQS[1:0]
Dc
Dd
De
Df
Dg
Dh
Da
Db
Da Db
D[15:0]
3
0
3
DM[1:0]
Row a
col a
NOP
PRCHG
NOP
ACT
NOP
WRITE
NOP
READ
BST
NOP
0
Data masked
SDCLK
A[12:0]
COMMAND
BA[1:0]
DQS[1:0]
Da Db
Da
Db
D[15:0]
3
0
3
DM[1:0]