Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Ficha De Dados
Códigos do produto
AT91SAM9N12-EK
485
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note:
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx registers are
fetched. The LLI.DMAC_DADDRx register location of the LLI, although fetched, is not used. The
DMAC_DADDRx register in the DMAC remains unchanged.
fetched. The LLI.DMAC_DADDRx register location of the LLI, although fetched, is not used. The
DMAC_DADDRx register in the DMAC remains unchanged.
16. Source and destination requests single and chunk DMAC transactions to transfer the buffer of data (assuming
non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in
the buffer and carries out the buffer transfer.
the buffer and carries out the buffer transfer.
17. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to the system memory at the
same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the loca-
tion of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only
DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE
fields have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the
buffer transfer has completed.
tion of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only
DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE
fields have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the
buffer transfer has completed.
Note:
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted,
then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the
transfer.
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted,
then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the
transfer.
18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from the
memory location pointed to by the current DMAC_DSCRx register, then automatically reprograms the
DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx
register is left unchanged. The DMAC transfer continues until the DMAC samples the DMAC_CTRLAx,
DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that described in Row 1 of
DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx
register is left unchanged. The DMAC transfer continues until the DMAC samples the DMAC_CTRLAx,
DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that described in Row 1 of
. The DMAC then knows that the previous buffer transferred was the last buffer in the
DMAC transfer.
The DMAC transfer might look like that shown in
. Note that the destination address is
decrementing.
Figure 32-16. DMAC Transfer with Linked List Source Address and Contiguous Destination Address
SADDR(2)
SADDR(1)
SADDR(0)
DADDR(2)
DADDR(1)
DADDR(0)
Buffer 2
Buffer 1
Buffer 0
Buffer 0
Buffer 1
Buffer 2
Address of
Source Layer
Address of
Destination Layer
Source Buffers
Destination Buffers