Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Ficha De Dados
Códigos do produto
AT91SAM9X25-EK
404
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 29-21.TDF Period in NCS Controlled Read Operation (TDF = 3)
29.11.2 TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of
the setup period of the next access to optimize the number of wait states cycle to insert.
the setup period of the next access to optimize the number of wait states cycle to insert.
shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
NCS
TDF = 3 clock cycles
tpacc
MCK
D[31:0]
NCS controlled read operation
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NBS2, NBS3,
A0,A1
NRD