Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Ficha De Dados

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

In window mode, the Early Warning interrupt is generated at the start of the open window period. In a typical application 
where the system is in sleep mode, it can use this interrupt to wake up and clear the Watchdog Timer, after which the 
system can perform other tasks or return to sleep mode.

Due to the asynchronicity between CLK_WDT_APB and GCLK_WDT some registers must be synchronized when 
accessed. A register can require:

z

Synchronization when written

z

Synchronization when read

z

Synchronization when written and read

z

No synchronization

When executing an operation that requires synchronization, the Synchronization Busy bit in the Status 
register(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The 
synchronization Ready interrupt can be used to signal when sync is complete. This can be accessed via the 
Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).

If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All 
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is 
stalled.

The following registers need synchronization when written:

z

Control register (CTRL)

z

Clear register (CLEAR)

Write-synchronization is denoted by the Write-Synchronized property in the register description.