Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Ficha De Dados

44

Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area (including 
flash and AHB RAM).

When the CRC32 command is issued from:

z

The internal range, the CRC32 can be operated at any memory location

z

The external range, the CRC32 operation is restricted; DATA, ADDR and LENGTH values are forced (see below)

The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320 
(reversed representation).

CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the 
size of the memory range into the Length register (LENGTH). Both must be word-aligned.

The initial value used for the CRC32 calculation must be written to the Data register. This value will usually be 
0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of 
separate memory blocks.

Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be 
complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for subsequent 
CRC32 calculations.

If the device is in protected state by the NVMCTRL security bit (refer to 

), it is only possible to 

calculate the CRC32 of the whole flash array when operated from the external address space. In most cases, this area 
will be the entire onboard non-volatile memory. The Address, Length and Data registers will be forced to predefined 
values once the CRC32 operation is started, and values written by the user are ignored. This allows the user to verify the 
contents of a protected device.

The actual test is started by writing a one in the 32-bit Cyclic Redundancy Check bit of the Control register (CTRL.CRC). 
A running CRC32 operation can be canceled by resetting the module (writing a one to CTRL.SWRST).

The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the Bus 
Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred.

The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake logic, 
accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit (refer to 

). The registers can be used to exchange data between the CPU and the debugger, during run time as well 

as in debug mode. This enables the user to build a custom debug protocol using only these registers. The DCC0 and 
DCC1 registers are accessible when the protected state is active. When the device is protected, however, it is not 
possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and the CPU is held 
under reset). Dirty bits in the status registers indicate whether a new value has been written in DCC0 or DCC1. These 
bits,DCC0D and DCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on 

0

ARRAY

CRC32 is restricted to the full flash array area (EEPROM emulation area not included)
DATA forced to 0xFFFFFFFF before calculation (no seed)

1

EEPROM

CRC32 of the whole EEPROM emulation area
DATA forced to 0xFFFFFFFF before calculation (no seed)

2-3

Reserved