Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Ficha De Dados
Códigos do produto
ATSAMD20-XPRO
465
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
27.8.10 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x0E
Reset:
0x00
Property:
-
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:4 – MCx: Match or Capture Channel x
This flag is set on the next CLK_TC_CNT cycle after a match with the compare condition or once CCx register
contain a valid capture value, and will generate an interrupt request if the corresponding Match or Capture Chan-
nel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is one.
This flag is set on the next CLK_TC_CNT cycle after a match with the compare condition or once CCx register
contain a valid capture value, and will generate an interrupt request if the corresponding Match or Capture Chan-
nel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is one.
Writing a zero to one of these bits has no effect.
Writing a one to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In capture mode, this flag is automatically cleared when CCx register is read.
z
Bit 3 – SYNCRDY: Synchronization Ready
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when the transition is caused by an enable or software reset, and will generate an interrupt request if the
Synchronization Ready Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.SYNCRDY) is one.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when the transition is caused by an enable or software reset, and will generate an interrupt request if the
Synchronization Ready Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.SYNCRDY) is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready interrupt flag
z
Bit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 1 – ERR: Error
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one, in which case there is nowhere to store the new capture.
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one, in which case there is nowhere to store the new capture.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Error interrupt flag.
z
Bit 0 – OVF: Overflow
This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt if
This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt if
INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
Bit
7
6
5
4
3
2
1
0
MC1
MC0
SYNCRDY
ERR
OVF
Access
R
R
R/W
R/W
R/W
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0