Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Ficha De Dados
Códigos do produto
ATSAMD20-XPRO
479
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
28.6.5 Differential and Single-Ended Conversions
The ADC has two conversion options: differential and single-ended. When measuring signals where the positive input is
always at a higher voltage than the negative input, the single-ended conversion should be used in order to have full 12-
bit resolution in the conversion, which has only positive values. The negative input must be connected to ground. This
ground could be the internal GND, IOGND or an external ground connected to a pin. Refer to
always at a higher voltage than the negative input, the single-ended conversion should be used in order to have full 12-
bit resolution in the conversion, which has only positive values. The negative input must be connected to ground. This
ground could be the internal GND, IOGND or an external ground connected to a pin. Refer to
for selection
details. If the positive input may go below the negative input, creating some negative results, the differential mode should
be used in order to get correct results. The configuration of the conversion is done in the Differential Mode bit in the
Control B register (CTRLB.DIFFMODE). These two types of conversion could be run in single mode or in free-running
mode. When set up in free-running mode, an ADC input will continuously sample and do new conversions. The
INTFLAG.RESRDY bit will be set at the end of each conversion.
be used in order to get correct results. The configuration of the conversion is done in the Differential Mode bit in the
Control B register (CTRLB.DIFFMODE). These two types of conversion could be run in single mode or in free-running
mode. When set up in free-running mode, an ADC input will continuously sample and do new conversions. The
INTFLAG.RESRDY bit will be set at the end of each conversion.
28.6.5.1 Conversion Timing
shows the ADC timing for a single conversion without gain. The writing of the ADC Start Conversion bit
(SWTRIG.START) or Start Conversion Event In bit (EVCTRL.STARTEI) must occur at least one CLK_ADC_APB cycle
before the CLK_ADC cycle on which the conversion starts. The input channel is sampled in the first half CLK_ADC
period. The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control
register (SAMPCTRL.SAMPLEN). Refer to
before the CLK_ADC cycle on which the conversion starts. The input channel is sampled in the first half CLK_ADC
period. The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control
register (SAMPCTRL.SAMPLEN). Refer to
Figure 28-3. ADC Timing for One Conversion in Differential Mode without Gain
Figure 28-4. ADC Timing for One Conversion in Differential Mode without Gain, but with Increased Sampling Time
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CLK_ ADC
START
SAMPLE
INT
Converting Bit
MS B
10
9
8
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5
4
3
2
1
LS B
1
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CLK_ ADC
START
SAMPLE
INT
Converting Bit
MS B
10
9
8
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5
4
3
2
1
LS B
9
10
11