Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Ficha De Dados

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

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The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to
a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair.
In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads
the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data
transfer. This is also known as a dual-access transfer.

The DMAC is programmed via the APB interface.

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1 AHB-Lite Master Interfaces

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DMA Module Supports the Following Transfer Schemes: Peripheral-to-Memory, Memory-to-Peripheral, 
Peripheral-to-Peripheral and Memory-to-Memory

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Source and Destination Operate independently on BYTE (8-bit), HALF-WORD (16-bit) and WORD (32-bit)

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Supports Hardware and Software Initiated Transfers

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Supports Multiple Buffer Chaining Operations

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Supports Incrementing/decrementing/fixed Addressing Mode Independently for Source and Destination

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Programmable Arbitration Policy, Modified Round Robin and Fixed Priority are Available

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Supports Specified Length and Unspecified Length AMBA AHB Burst Access to Maximize Data Bandwidth

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AMBA APB Interface Used to Program the DMA Controller

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4 DMA Channels 16 External Request Lines 

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Embedded FIFO 

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Channel Locking and Bus Locking Capability