Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Ficha De Dados

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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7. Select the master clock and processor clock

The master clock and the processor clock are configurable via the PMC_MCKR.
The CSS field is used to select the clock source of the master clock and processor clock dividers. By default, 

the selected clock source is the main clock.
The PRES field is used to define the processor clock and master clock prescaler. The user can choose 

between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency 

divided by the PRES value.
Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR. 

This can be done either by polling MCKRDY in the PMC_SR or by waiting for the interrupt line to be raised if 

the associated interrupt source (MCKRDY) has been enabled in the PMC_IER.
The PMC_MCKR must not be programmed in a single write operation. The programming sequence for 

PMC_MCKR is as follows:



If a new value for CSS field corresponds to PLL clock,

̶

Program the PRES field in PMC_MCKR.

̶

Wait for the MCKRDY bit to be set in PMC_SR.

̶

Program the CSS field in PMC_MCKR.

̶

Wait for the MCKRDY bit to be set in PMC_SR.



If a new value for CSS field corresponds to main clock or slow clock,

̶

Program the CSS field in PMC_MCKR.

̶

Wait for the MCKRDY bit to be set in the PMC_SR.

̶

Program the PRES field in PMC_MCKR.

̶

Wait for the MCKRDY bit to be set in PMC_SR.

If at some stage parameters CSS or PRES is modified, the MCKRDY bit goes low to indicate that the master 

clock and the processor clock are not yet ready. The user must wait for MCKRDY bit to be set again before 

using the master and processor clocks.

Note:

IF PLLx clock was selected as the master clock and the user decides to modify it by writing in CKGR_PLLxR, the 

MCKRDY flag will go low while PLLx is unlocked. Once PLLx is locked again, LOCKx goes high and MCKRDY is set.

While PLLx is unlocked, the master clock selection is automatically changed to slow clock for PLLA and main clock for 

PLLB. For further information, see 

. 

Code Example: 

write_register(PMC_MCKR,0x00000001)

wait (MCKRDY=1)

write_register(PMC_MCKR,0x00000011)

wait (MCKRDY=1)

The master clock is main clock divided by 2.

8. Select the programmable clocks

Programmable clocks are controlled via registers, PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. 3 programmable 

clocks can be used. The PMC_SCSR indicates which programmable clock is enabled. By default all 

programmable clocks are disabled.
PMC_PCKx registers are used to configure programmable clocks.
The CSS field is used to select the programmable clock divider source. Several clock options are available: 

main clock, slow clock, master clock, PLLACK, PLLBCK. The slow clock is the default clock source.