Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Ficha De Dados

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a

new compare 0. 
1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.

If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. 

When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG 

(Receive Sync Data) reception.

This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no 

PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.

0

CONTINUOUS

None

1

EN_RF_LOW

Receive Clock enabled only if RF Low

2

EN_RF_HIGH

Receive Clock enabled only if RF High

0

CONTINUOUS

Continuous, as soon as the receiver is enabled, and immediately 

after the end of transfer of the previous data.

1

TRANSMIT

Transmit start

2

RF_LOW

Detection of a low level on RF signal

3

RF_HIGH

Detection of a high level on RF signal

4

RF_FALLING

Detection of a falling edge on RF signal

5

RF_RISING

Detection of a rising edge on RF signal

6

RF_LEVEL

Detection of any level change on RF signal

7

RF_EDGE

Detection of any edge on RF signal

8

CMP_0

Compare 0