Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Ficha De Dados

32072H–AVR32–10/2012

Register Name:

MR

Access Type:

Read/Write

0x00

Reset Value:

0x00000000

This field defines the command issued by the SDRAMC when the SDRAM device is accessed.

31

30

29

28

27

26

25

24

-

-

-

-

-

-

-

-

23

22

21

20

19

18

17

16

-

-

-

-

-

-

-

-

15

14

13

12

11

10

9

8

-

-

-

-

-

-

-

-

7

6

5

4

3

2

1

0

-

-

-

-

-

MODE

0

Normal mode. Any access to the SDRAM is decoded normally.

1

The SDRAMC issues a “NOP” command when the SDRAM device is accessed regardless of the cycle.

2

The SDRAMC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of 
the cycle.

3

The SDRAMC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the 
cycle. This command will load the CR.CAS field into the SDRAM device Mode Register. All the other parameters 
of the SDRAM device Mode Register will be set to zero (burst length, burst type, operating mode, write burst 
mode...).

4

The SDRAMC issues an “Auto Refresh” command when the SDRAM device is accessed regardless of the cycle. 
Previously, an “All Banks Precharge” command must be issued.

5

The SDRAMC issues an “Extended Load Mode Register” command when the SDRAM device is accessed 
regardless of the cycle. This command will load the LPR.PASR, LPR.DS, and LPR.TCR fields into the SDRAM 
device Extended Mode Register. All the other bits of the SDRAM device Extended Mode Register will be set to 
zero.

6

Deep power-down mode. Enters deep power-down mode.