Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Ficha De Dados
Códigos do produto
AT32UC3A3-XPLD
508
32072H–AVR32–10/2012
AT32UC3A3
24. Synchronous Serial Controller (SSC)
Rev: 3.2.0.2
24.1
Features
•
Provides serial synchronous communication links used in audio and telecom applications
•
Independent receiver and transmitter, common clock divider
•
Interfaced with two Peripheral DMA Controller channels to reduce processor overhead
•
Configurable frame sync and data length
•
Receiver and transmitter can be configured to start automatically or on detection of different
events on the frame sync signal
•
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
24.2
Overview
The Synchronous Serial Controller (SSC) provides a synchronous communication link with
external devices. It supports many serial synchronous communication protocols generally used
in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.
external devices. It supports many serial synchronous communication protocols generally used
in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC consists of a receiver, a transmitter, and a common clock divider. Both the receiver
and the transmitter interface with three signals:
and the transmitter interface with three signals:
• the TX_DATA/RX_DATA signal for data
• the TX_CLOCK/RX_CLOCK signal for the clock
• the TX_FRAME_SYNC/RX_FRAME_SYNC signal for the frame synchronization
The transfers can be programmed to start automatically or on different events detected on the
Frame Sync signal.
Frame Sync signal.
The SSC’s high-level of programmability and its two dedicated Peripheral DMA Controller chan-
nels of up to 32 bits permit a continuous high bit rate data transfer without processor
intervention.
nels of up to 32 bits permit a continuous high bit rate data transfer without processor
intervention.
Featuring connection to two Peripheral DMA Controller channels, the SSC permits interfacing
with low processor overhead to the following:
with low processor overhead to the following:
• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader