Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Ficha De Dados

32072H–AVR32–10/2012

the Fractional Part field in BRGR (BRGR.FP), and is activated by giving it a non-zero value. The
resolution is one eighth of CD. The resulting baud rate is calculated using the following formula:

The modified architecture is shown in 

.

Figure 25-14. Fractional Baud Rate Generator

If the USART is configured to operate in synchronous mode (MR.SYNC is one), the selected
clock is divided by BRGR.CD. This does not apply when the external clock CLK is selected. 

When CLK is selected, the frequency of the external clock must be at least 4.5 times lower than
the system clock, and when either CLK or CLK_USART/DIV are selected, BRGR.CD must be
even to ensure a 50/50 duty cycle. If CLK_USART is selected, the generator ensures this
regardless of value.

The USART features an RS485 mode, supporting line driver control. This supplements normal
synchronous and asynchronous mode by driving the RTS pin high when the transmitter is oper-
ating. The RTS pin level is the inverse of the CSR.TXEMPTY value. The RS485 mode is
enabled by writing 0x1 to MR.MODE. A typical connection to a RS485 bus is shown in 

.

8 2

–

(

) CD FP

8

-------

+

⎝

⎠

⎛

⎞

⎝

⎠

⎛

⎞

--------------------------------------------------------------------

=

USCLKS

CD

Modulus

Control

FP

FP

CD

glitch-free

logic

16-bit Counter

OVER

SYNC

Sampling

Divider

CLK_USART

CLK_USART/DIV

Reserved

CLK

CLK

BaudRate

Clock

Sampling

Clock

SYNC

USCLKS = 3

>1

1

2

3

0

0

1

0

1

1

0

0

--------------------------------------

=