Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Ficha De Dados

32072H–AVR32–10/2012

6.

When Data transfer is completed, host processor shall terminate the boot stream by 
writing the MCI_CMDR register with SPCMD field set to BOOTEND.

1.

Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR regis-
ter. The BOOT_BUS_WIDTH field in the device Extended CSD register must be set 
accordingly.

2.

Set the bytecount to 512 bytes and the blockcount to the desired number of block, writ-
ing BLKLEN and BCNT fields of the MCI_BLKR Register.

3.

Enable DMA transfer in the MCI_DMA register.

4.

Configure DMA controller, program the total amount of data to be transferred and 
enable the relevant channel.

5.

Issue the Boot Operation Request command by writing to the MCI_CMDR register with 
SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.

6.

DMA controller copies the boot partition to the memory.

7.

When DMA transfer is completed, host processor shall terminate the boot stream by 
writing the MCI_CMDR register with SPCMD field set to BOOTEND.

The SR.XFRDONE bit indicates exactly when the read or write sequence is finished.

During a read access, the SR.XFRDONE bit behaves as shown in 

.

Figure 31-13. SR.XFRDONE During a Read Access

CMD line

MCI read CMD

Card response

CMDRDY flag

Data

1st Block

Last Block

Not busy flag

XFRDONE flag

The CMDRDY flag is released 8 t

bit 

lafter the end of the card response.