Linear Technology LTC2314-14, 14-Bit, 4.5Msps Serial SAR ADC with 20ppm/C (Max) Internal Reference in TSOT-8 (Req DC590 or DC718) Linear T DC1563A-F Ficha De Dados
Códigos do produto
DC1563A-F
LTC2314-14
5
231414fa
ADC TIMING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency
(Notes 7, 8)
l
4.5
MHz
f
SCK
Shift Clock Frequency
(Notes 7, 8)
l
87.5
MHz
t
SCK
Shift Clock Period
l
11.4
ns
t
THROUGHPUT
Minimum Throughput Time, t
ACQ
+ t
CONV
l
222
ns
t
CONV
Conversion Time
l
182
ns
t
ACQ
Acquisition Time
l
40
ns
t
1
Minimum CS Pulse Width
(Note 7)
l
10
ns
t
2
SCK
↔
Setup Time After CS
↓
(Note 7)
l
5
ns
t
3
SDO Enable Time After CS
↓
(Notes 7, 8)
l
10
ns
t
4
SDO Data Valid Access Time after SCK
↓
(Notes 7, 8, 9)
l
9.1
ns
t
5
SCLK Low Time
l
4.5
ns
t
6
SCLK High Time
l
4.5
ns
t
7
SDO Data Valid Hold Time After SCK
↓
(Notes 7, 8, 9)
l
1
ns
t
8
SDO into Hi-Z State Time After 16th SCK
↓
(Notes 7, 8, 10)
l
3
10
ns
t
9
SDO into Hi-Z State Time After CS
↑
(Notes 7, 8, 10)
l
3
10
ns
t
10
CS
↑ Setup Time After 14th SCK↓
(Note 7)
l
5
ns
Latency
l
1 Cycle Latency
t
WAKE
_
NAP
Power-Up Time from Nap Mode
See Nap Mode Section
50
ns
t
WAKE
_
SLEEP
Power-Up Time from Sleep Mode
See Sleep Mode Section
1.1
ms
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to ground.
Note 3. When these pin voltages are taken below ground or above V
Note 2. All voltage values are with respect to ground.
Note 3. When these pin voltages are taken below ground or above V
DD
(A
IN
, REF) or OV
DD
(SCK, CS, SDO) they will be clamped by internal
diodes. This product can handle input currents up to 100mA below ground
or above V
DD
or OV
DD
without latch-up.
Note 4. V
DD
= 5V, OV
DD
= 2.5V, f
SMPL
= 4.5MHz, f
SCK
= 87.5MHz, A
IN
=
–1dBFS and internal reference unless otherwise noted.
Note 5. Integral nonlinearity is defined as the deviation of a code from a
Note 5. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6. Typical RMS noise at code transitions.
Note 7. Parameter tested and guaranteed at OV
Note 7. Parameter tested and guaranteed at OV
DD
= 2.5V. All input signals
are specified with t
r
= t
f
= 1nS (10% to 90% of OV
DD
) and timed from a
voltage level of OV
DD
/2.
Note 8. All timing specifications given are with a 10pF capacitance load.
Load capacitances greater than this will require a digital buffer.
Note 9. The time required for the output to cross the V
Note 9. The time required for the output to cross the V
IH
or V
IL
voltage.
Note 10. Guaranteed by design, not subject to test.
Note 11. Recommended operating conditions.