Linear Technology LTC2377-18 with LTC6655-5/LT6350: 18-Bit, 500ksps, SAR ADC with 102dB SNR. Req DC718 or DC590 DC1783A- DC1783A-G Ficha De Dados

LTC2377-18

5

237718f

l

t

SCK

SCK Period

(Notes 11, 12)

l

10

ns

t

SCKH

SCK High Time

l

4

ns

t

SCKL

SCK Low Time

l

4

ns

t

SSDISCK

SDI Setup Time From SCK

↑

(Note 11)

l

4

ns

t

HSDISCK

SDI Hold Time From SCK

↑

(Note 11)

l

1

ns

t

SCKCH

SCK Period in Chain Mode

t

SCKCH

 = t

SSDISCK

 + t

DSDO 

(Note 11)

l

13.5

ns

t

DSDO

SDO Data Valid Delay from SCK

↑

C

L

 = 20pF (Note 11)

l

9.5

ns

t

HSDO

SDO Data Remains Valid Delay from SCK

↑

C

L

 = 20pF (Note 10)

l

1

ns

t

DSDOBUSYL

SDO Data Valid Delay from BUSY

↓

C

L

 = 20pF (Note 10)

l

5

ns

t

EN

Bus Enable Time After RDL

↓

(Note 11)

l

16

ns

t

DIS

Bus Relinquish Time After RDL

↑ 

(Note 11)

l

13

ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings 
may cause permanent damage to the device. Exposure to any Absolute 
Maximum Rating condition for extended periods may effect device 
reliability and lifetime.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground or above REF or 
OV

DD

, they will be clamped by internal diodes. This product can handle 

input currents up to 100mA below ground or above REF or OV

DD

 without 

latch-up.

Note 4: V

DD

 = 2.5V, OV

DD

 = 2.5V, REF = 5V, V

CM

 = 2.5V, f

SMPL

 = 500kHz, 

REF/DGC = V

REF

.

Note 5: Recommended operating conditions.

Note 6: Integral nonlinearity is defined as the deviation of a code from a 
straight line passing through the actual endpoints of the transfer curve. 
The deviation is measured from the center of the quantization band.

Note 7: Bipolar zero-scale error is the offset voltage measured from 
–0.5LSB when the output code flickers between 00 0000 0000 0000 0000 
and 11 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of 
–FS or +FS untrimmed deviation from ideal first and last code transitions 
and includes the effect of offset error.

Note 8: All specifications in dB are referred to a full-scale ±5V input with a 
5V reference voltage.

Note 9: f

SMPL

 = 500kHz, I

REF

 varies proportionately with sample rate.

Note 10: Guaranteed by design, not subject to test.

Note 11: Parameter tested and guaranteed at OV

DD

 = 1.71V, OV

DD

 = 2.5V 

and OV

DD

 = 5.25V.

Note 12: t

SCK

 of 10ns maximum allows a shift clock frequency up to 

100MHz for rising capture.

0.8*OV

DD

0.2*OV

DD

50%

50%

237718 F01

0.2*OV

DD

0.8*OV

DD

0.2*OV

DD

0.8*OV

DD

t

DELAY

t

WIDTH

t

DELAY