Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Ficha De Dados

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
Figure 16-2.
Counter Unit Block Diagram
Signal description (internal signals):
Count
Increment or decrement TCNT1 by 1.
Direction
Select between increment and decrement.
Clear
Clear TCNT1 (set all bits to zero).
clk
T
1
Timer/Counter clock.
TOP
Signalize that TCNT1 has reached maximum value.
BOTTOM
Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper 
eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can 
only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU 
accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value 
when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. 
This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. 
It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is 
counting that will give unpredictable results. The special cases are described in the sections where they are of 
importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer 
clock
 (clk
T
1
). The clk
T
1
 can be generated from an external or internal clock source, selected by the Clock Select 
bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value 
can be accessed by the CPU, independent of whether clk
T
1
 is present or not. A CPU write overrides (has priority 
over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located 
in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between 
how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. 
For more details about advanced counting sequences and waveform generation, see 
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 
bits. TOV1 can be used for generating a CPU interrupt.
16.6
Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-
stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied 
via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate 
frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for 
creating a log of the events.
TEMP (8-bit)
DATA BUS 
(8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit)
TCNTnL (8-bit)
Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP
BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn