Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Ficha De Dados
Códigos do produto
MEGA328P-XMINI
130
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and
COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
16.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T1
) is therefore shown as a clock enable
signal in the following figures. The figures include information on when Interrupt Flags are set, and when the
OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering).
OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering).
shows a timing diagram for the setting of OCF1x.
Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
shows the same timing data, but with the prescaler enabled.
Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
clk_I/O
/8)
shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the
same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies
for modes that set the TOV1 Flag at BOTTOM.
same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies
for modes that set the TOV1 Flag at BOTTOM.
clk
Tn
(clk
I/O
/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)