Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Ficha De Dados
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MEGA328P-XMINI
143
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the
figure.
figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2
pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status
Register (ASSR). The Clock Select logic block controls which clock source he Timer/Counter uses to increment
(or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the
Clock Select logic is referred to as the timer clock (clk
pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status
Register (ASSR). The Clock Select logic block controls which clock source he Timer/Counter uses to increment
(or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the
Clock Select logic is referred to as the timer clock (clk
T2
).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or
variable frequency output on the Output Compare pins (OC2A and OC2B). See
value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or
variable frequency output on the Output Compare pins (OC2A and OC2B). See
for details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be
used to generate an Output Compare interrupt request.
18.2.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value and so on.
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value and so on.
The definitions in
are also used extensively throughout the section.
Table 18-1.
Definitions
18.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The
clock source clk
clock source clk
T2
is by default equal to the MCU clock, clk
I/O
. When the AS2 bit in the ASSR Register is written
to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For
details on asynchronous operation, see
details on asynchronous operation, see
. For details on
clock sources and prescaler, see
.
18.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
shows a block diagram of the counter and its surrounding environment.
Figure 18-2.
Counter Unit Block Diagram
BOTTOM
The counter reaches the BOTTOM when it becomes zero (0x00).
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is
dependent on the mode of operation.
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is
dependent on the mode of operation.
DATA BUS
TCNTn
Control Logic
count
TOVn
(Int.Req.)
(Int.Req.)
top
bottom
direction
clear
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clk
I/O
clk
Tn