Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Ficha De Dados

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
transmitting application must enter receive mode and free the communication bus immediately after completing 
the transmission.
When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART Transmit Complete 
Interrupt will be executed when the TXCn Flag becomes set (provided that global interrupts are enabled). When 
the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXCn Flag, this 
is done automatically when the interrupt is executed.
20.6.4 Parity Generator
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPMn1 = 1), 
the transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is 
sent.
20.6.5 Disabling the Transmitter
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending 
transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain 
data to be transmitted. When disabled, the Transmitter will no longer override the TxDn pin.
20.7
Data Reception – The USART Receiver
The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the
UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn pin is overridden 
by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and 
frame format must be set up once before any serial reception can be done. If synchronous operation is used, 
the clock on the XCKn pin will be used as transfer clock.
20.7.1 Receiving Frames with 5 to 8 Data Bits
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be 
sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register until the first stop bit of a 
frame is received. A second stop bit will be ignored by the Receiver. When the first stop bit is received, i.e., a 
complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved 
into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location.
The following code example shows a simple USART receive function based on polling of the Receive Complete 
(RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the 
UDRn will be masked to zero. The USART has to be initialized before the function can be used.