Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Ficha De Dados

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to 
ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next 
can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in 
Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock 
frequency while still ensuring stable operation. Refer to 

 for details.

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be 
programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock 
also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is 
programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on 
CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output. 

ATmega48A/PA/88A/PA/168A/PA/328/P uses the same crystal oscillator for Low-frequency Oscillator and 
Timer/Counter Oscillator. See 

 for details on the oscillator and 

crystal requirements.

ATmega48A/PA/88A/PA/168A/PA/328/P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with 
XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the 
oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be used when the 
Calibrated Internal RC Oscillator is selected as system clock source.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic 
one. See 

 for further description on selecting external 

clock as input instead of a 32.768kHz watch crystal.

The ATmega48A/PA/88A/PA/168A/PA/328/P has a system clock prescaler, and the system clock can be 
divided by setting the 

7. This feature can be used to decrease 

the system clock frequency and the power consumption when the requirement for processing power is low. This 
can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous 
peripherals. clk

I/O

, clk

ADC

, clk

CPU

, and clk

FLASH

 are divided by a factor as shown in 

.

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the 
clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency 
corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple 
counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the 
CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were 
readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. 

BOD enabled

6 CK

14CK

00

Fast rising power

6 CK

14CK + 4.1ms

01

Slowly rising power

6 CK

14CK + 65ms

10

Reserved

11