Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Ficha De Dados
Códigos do produto
MEGA328P-XMINI
6
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
2.
Overview
The ATmega48A/PA/88A/PA/168A/PA/328/P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the
system designer to optimize power consumption versus processing speed.
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the
system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
PORT C (7)
PORT B (8)
PORT D (8)
USART 0
8bit T/C 2
16bit T/C 1
8bit T/C 0
A/D Conv.
Internal
Bandgap
Analog
Comp.
SPI
TWI
SRAM
Flash
EEPROM
Watchdog
Oscillator
Watchdog
Timer
Oscillator
Circuits /
Clock
Generation
Power
Supervision
POR / BOD &
RESET
VCC
GND
PROGRAM
LOGIC
debugWIRE
2
GND
AREF
AVCC
D
ATA
B
U
S
ADC[6..7]
PC[0..6]
PB[0..7]
PD[0..7]
6
RESET
XTAL[1..2]
CPU