On Semiconductor NCL30000 Evaluation Board NCL30000LED1GEVB NCL30000LED1GEVB Ficha De Dados

insulated wire is selected for compliance with safety agency
isolation requirements.

The primary bias winding must supply 10.2 V to maintain

NCL30000 operation. The minimum secondary voltage is
12 V and with 24 turns this means the bias winding needs
20.4 turns. Select 22 turns to meet the minimum.

For maximum primary to secondary coupling, the primary

winding will be split in two equal sections with the
secondary winding placed in between. The bias winding is
wound on top of the second half of the primary winding.

The NCL30000 controller drives an external power FET

controlling the current in the flyback transformer primary.
The demonstration board was designed to accept the surface
mount DPAK or through-hole TO−220 power packages. The
17.5 W target application in 50C ambient works well with

a DPAK package. The 800 V 2 A rated SPD02N80C3 was
chosen.

Maximum primary current was calculated as 1.11 A. The

NCL30000 has a 0.5 V over-current protection threshold. To
allow for 25% margin, a minimum sense resistor of 0.348 

W

is required. A standard 0.33 

W resistor will be selected. The

current sense resistor is placed in the source lead of the
power FET and coupled to the controller with a 100 

W

resistor. This resistance in conjunction with the inherent
capacitance of the pin filters high frequency noise. In
addition, a leading edge blanking (LEB) function is included
in the controller. This feature avoids spurious activation of
the over-current protection when the power FET is first
turned on.

Maximum FET switch on-time is controlled by the C

t

capacitor. Limiting the maximum on-time reduces
component stress in transient situations. The formula below
establishes the capacitor value based on charging current of
297 

mA and maximum voltage threshold of 4.775. The

symbol 

h' represents the effective efficiency of the power

transformer stage and secondary losses. It will always be
greater than the measured wall plug efficiency which
includes losses in the EMI filter and primary side compents.

(eq. 2)

C

t

[

ǒ

4 @ L

pri

@ P

out

@ I

charge

Ǔ

ǒ

hȀ @ V

pk

2

@ V

CT(max)

Ǔ

@

ǒ

V

pk

N @ V

out

) 1

Ǔ

C

t

[

ǒ

4 @ 0.00157 @ 17.5 @ 297 mA

Ǔ

ǒ

0.95 @

ǒ

2

Ǹ @ 90

Ǔ

2

@ 4.775 V

Ǔ

@

ǒ

2

Ǹ @ 90

3.83 @ 50

) 1

Ǔ

C

t

[ 740 pF

The C

t

 equation is an approximation for simplification. For

example, V

pk

 assumes no losses through the diode rectifier

bridge and EMI filter. This establishes an initial starting point
for the C

t

 capacitor and further optimization may be needed.

For this design, 820 pF was used as the final value.

As previously discussed, a high power factor isolated

single-stage converter processes power in a sine squared
manner at twice the line frequency. Energy storage must be
provided on the isolated secondary output just as in normal
flyback converters however significantly more storage
capacity is required due to the sine squared energy transfer
characteristic. Capacitors are used to store energy as the
peak of the 100 or 120 Hz rectified sine wave delivers
maximum power and then releases the stored energy to the
load when the rectified sine wave falls below the target
output power. As the storage capacitor charges and
discharges some ripple current is developed in the LED load.
The magnitude of ripple voltage is controlled by the amount
of filter capacitance and the impedance of the LED string. In
this 350 mA application, two 470 

mF capacitors are

sufficient to provide 30% ripple.

High grade electrolytic capacitors should be selected to

match driver lifetime with that of the LEDs. Higher
temperature rated capacitors enhance lifetime for an optimal
solution. To meet ripple requirements in single stage
converters filter capacitance is generally high enough that
capacitor ripple current is well below device ratings.

The average mode feedback compensation is

intentionally set to a low frequency as described in the
feedback section. The relatively large feedback
compensation capacitor must charge to normal operating
voltage after initial power up which introduces significant
delay in regulation. Minimizing the required voltage change
on the compensation capacitor allows the feedback loop to
take control of the output quicker therefore reducing
over-current conditions. Maintaining a low bias voltage
reduces the required change in compensation capacitor
voltage. For this example, a bipolar transistor and 5.6 V
zener diode are employed to provide bias voltage of about
5 V. This bias transistor minimizes power loss and allows the
LED driver to operate over a very wide range of output
voltage. This circuit will support as few as 4 LEDs and up
to 15 LEDs.

The secondary bias can be optimized if the application

uses a specific number of LEDs. Fewer components and
better efficiency can be realized by limiting the output
voltage range and adding a secondary bias winding to the
transformer.

The LED driver behaves like a current source where the

output voltage is determined by the forward voltage of the
LED string. As such, some protection is required to prevent
damage in the event of an open LED situation. Transistor
(Q5) and zener diode (D12) affords the necessary protection.
A 56 V zener is used in this design example.