STMicroelectronics 400 W FOT-controlled PFC pre-regulator with the L6563S EVL6563S-400W EVL6563S-400W Ficha De Dados
Códigos do produto
EVL6563S-400W
AN2994
Test results and significant waveforms
Doc ID 15796 Rev 2
13/38
On both the drain voltage traces reported in
, close to the zero
crossing points of the sine wave it is possible to note the action of the THD optimizer
embedded in the L6563S. This optimizer is a circuit that minimizes the conduction’s dead-
angle occurring at the AC’s input current near the zero-crossings of the line voltage
(crossover distortion). In this way, the THD of the current is considerably reduced. A major
cause of this distortion is the inability of the system to transfer energy effectively when the
instantaneous line voltage is very low. This effect is magnified by the high-frequency filter
capacitor placed after the bridge rectifier, which retains some residual voltage that causes
the diodes of the bridge rectifier to be reverse-biased and the input current flow to
temporarily stop. To overcome this issue, the device forces the PFC pre-regulator to process
more energy near the line voltage’s zero-crossing, as compared to that commanded by the
control loop.
embedded in the L6563S. This optimizer is a circuit that minimizes the conduction’s dead-
angle occurring at the AC’s input current near the zero-crossings of the line voltage
(crossover distortion). In this way, the THD of the current is considerably reduced. A major
cause of this distortion is the inability of the system to transfer energy effectively when the
instantaneous line voltage is very low. This effect is magnified by the high-frequency filter
capacitor placed after the bridge rectifier, which retains some residual voltage that causes
the diodes of the bridge rectifier to be reverse-biased and the input current flow to
temporarily stop. To overcome this issue, the device forces the PFC pre-regulator to process
more energy near the line voltage’s zero-crossing, as compared to that commanded by the
control loop.
This results in minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge. Essentially, the circuit
artificially increases the ON time of the power switch with a positive offset added to the
output of the multiplier in the proximity of the line voltage zero crossing. This offset is
reduced as the instantaneous line voltage increases, so that it becomes negligible as the
line voltage moves towards the top of the sinusoid, and it is modulated by the voltage on the
V
discharging the high-frequency filter capacitor after the bridge. Essentially, the circuit
artificially increases the ON time of the power switch with a positive offset added to the
output of the multiplier in the proximity of the line voltage zero crossing. This offset is
reduced as the instantaneous line voltage increases, so that it becomes negligible as the
line voltage moves towards the top of the sinusoid, and it is modulated by the voltage on the
V
FF
pin so as to have little offset at low lines, where the transfer of energy at zero crossings
is typically quite good, and a larger offset at high lines, where the energy transfer gets
worse.
worse.
To get the maximum benefit from the THD optimizer circuit, the high-frequency filter
capacitors after the bridge rectifier should be minimized, compatibly with EMI filtering needs.
A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in
itself, thus reducing the effectiveness of the optimizer circuit.
capacitors after the bridge rectifier should be minimized, compatibly with EMI filtering needs.
A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in
itself, thus reducing the effectiveness of the optimizer circuit.
Figure 19.
EVL6563S-400W inductor current
ripple envelope at 230 Vac, 50 Hz,
full load
ripple envelope at 230 Vac, 50 Hz,
full load
Figure 20.
EVL6563S-400W inductor current
ripple (detail) at 230 Vac, 50 Hz,
full load
ripple (detail) at 230 Vac, 50 Hz,
full load
CH1: Q1/Q2 drain voltage
CH1: Q1/Q2 drain voltage
CH2: MULT voltage - pin #3
CH2: MULT voltage - pin #3
CH4: L4 inductor current ripple envelope
CH4: L4 inductor current ripple envelope