STMicroelectronics 19V - 90W Adapter with PFC for Laptop computers using the L6563H and L6699 EVL6699-90WADP EVL6699-90WADP Ficha De Dados
Códigos do produto
EVL6699-90WADP
Pin connections
L6699
8/38
Doc ID 022835 Rev 2
Figure 3.
Typical system block diagram
10
GND
Chip ground. Current return for both the low-side gate-drive current and the
bias current of the IC. All of the ground connections of the bias components
should be tied to a track going to this pin and kept separate from any pulsed
current return.
bias current of the IC. All of the ground connections of the bias components
should be tied to a track going to this pin and kept separate from any pulsed
current return.
11
LVG
Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.8 A
min. sink peak current to drive the lower MOSFET of the half bridge leg. The pin
is actively pulled to GND during UVLO.
min. sink peak current to drive the lower MOSFET of the half bridge leg. The pin
is actively pulled to GND during UVLO.
12
V
CC
Supply voltage of both the signal part of the IC and the low-side gate driver.
Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful to
obtain a clean bias voltage for the signal part of the IC.
Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful to
obtain a clean bias voltage for the signal part of the IC.
13
N.C.
High voltage spacer. The pin is not internally connected to isolate the high
voltage pin and ease compliance with safety regulations (creepage distance) on
the PCB.
voltage pin and ease compliance with safety regulations (creepage distance) on
the PCB.
14
OUT
High-side gate-drive floating ground. Current return for the high-side gate-drive
current. Lay out the connection of this pin carefully to avoid too large spikes
below ground.
current. Lay out the connection of this pin carefully to avoid too large spikes
below ground.
15
HVG
High-side floating gate-drive output. The driver is capable of 0.3 A min. source
and 0.8 A min. sink peak current to drive the upper MOSFET of the half bridge
leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not
floating during UVLO.
and 0.8 A min. sink peak current to drive the upper MOSFET of the half bridge
leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not
floating during UVLO.
16
V
BOOT
High-side gate-drive floating supply voltage. The bootstrap capacitor connected
between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap
diode driven in-phase with the low-side gate-drive. This patented structure
replaces the normally used external diode.
between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap
diode driven in-phase with the low-side gate-drive. This patented structure
replaces the normally used external diode.
Table 4.
Pin functions (continued)
N.
Name
Function
!-V
6
INAC
6OUTDC
2ESON ANT
0&#gS
0&#
LOAD
ENERGY
0&#
2%3/.!.4
(!,&
"2)$'%
-)$0/).4
, !
,
,
,
3(
4(