STMicroelectronics L6563H 100 W TM PFC demonstration board EVL6563H-100W EVL6563H-100W Ficha De Dados
Códigos do produto
EVL6563H-100W
AN3063
Test results and significant waveforms
Doc ID 16261 Rev 3
13/33
power factor. On both the drain voltage traces, close to the zero-crossing points of the sine
wave, it is possible to note the action of the THD optimizer embedded in the L6563H. It is a
circuit that minimizes the conduction dead-angle of the AC input current near the zero-
crossings of the line voltage (crossover distortion). In this way, the THD (total harmonic
distortion) of the current is considerably reduced. A major cause of this distortion is the
inability of the system to transfer energy effectively when the instantaneous line voltage is
very low. This effect is magnified by the high-frequency filter capacitor placed after the
bridge rectifier, which retains some residual voltage that causes the diodes of the bridge
rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this
issue the device forces the PFC pre-regulator to process more energy near the line voltage
zero-crossings as compared to that commanded by the control loop. This results in both
minimizing the time interval where energy transfer is lacking and fully discharging the high-
frequency filter capacitor after the bridge. Essentially, the circuit artificially increases the ON-
time of the power switch with a positive offset added to the output of the multiplier in the
proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line
voltage increases, so that it becomes negligible as the line voltage moves toward the top of
the sinusoid. Furthermore the offset is modulated by the voltage on the V
wave, it is possible to note the action of the THD optimizer embedded in the L6563H. It is a
circuit that minimizes the conduction dead-angle of the AC input current near the zero-
crossings of the line voltage (crossover distortion). In this way, the THD (total harmonic
distortion) of the current is considerably reduced. A major cause of this distortion is the
inability of the system to transfer energy effectively when the instantaneous line voltage is
very low. This effect is magnified by the high-frequency filter capacitor placed after the
bridge rectifier, which retains some residual voltage that causes the diodes of the bridge
rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this
issue the device forces the PFC pre-regulator to process more energy near the line voltage
zero-crossings as compared to that commanded by the control loop. This results in both
minimizing the time interval where energy transfer is lacking and fully discharging the high-
frequency filter capacitor after the bridge. Essentially, the circuit artificially increases the ON-
time of the power switch with a positive offset added to the output of the multiplier in the
proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line
voltage increases, so that it becomes negligible as the line voltage moves toward the top of
the sinusoid. Furthermore the offset is modulated by the voltage on the V
FF
pin so as to
have little offset at low line, where energy transfer at zero-crossings is typically quite good,
and a larger offset at high line where the energy transfer gets worse.
and a larger offset at high line where the energy transfer gets worse.
To obtain maximum benefit from the THD optimizer circuit, the high-frequency filter
capacitors after the bridge rectifier should be minimized, compatibly with EMI filtering needs.
A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in
itself, thus reducing the effectiveness of the optimizer circuit.
capacitors after the bridge rectifier should be minimized, compatibly with EMI filtering needs.
A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in
itself, thus reducing the effectiveness of the optimizer circuit.
the detail of the waveforms at switching frequency allows measuring the
operating frequency and the current peak at top of the input sine wave during operation at
100 Vac and 230 Vac. The multiplier waveform has been captured as a reference.
100 Vac and 230 Vac. The multiplier waveform has been captured as a reference.
Figure 12.
EVL6563H-100W TM PFC: Vds and
inductor current at 100 Vac, 50 Hz,
full load
inductor current at 100 Vac, 50 Hz,
full load
Figure 13.
EVL6563H-100W TM PFC: Vds and
inductor current at 100 Vac, 50 Hz,
full load (detail)
inductor current at 100 Vac, 50 Hz,
full load (detail)
CH1: Q1 drain voltage
CH2: MULT voltage - Pin #3
CH4: L2 inductor current
CH4: Q1 drain voltage
CH2: MULT voltage - pin #3
CH1: L2 inductor current