STMicroelectronics L6563H 100 W TM PFC demonstration board EVL6563H-100W EVL6563H-100W Ficha De Dados
Códigos do produto
EVL6563H-100W
AN3063
Layout hints
Doc ID 16261 Rev 3
25/33
5 Layout
hints
The layout of any converter is a very important phase in the design process needing
attention by the design engineers like any other design phase. Even if it the layout phase
sometimes looks time-consuming, a good layout does indeed save time during the
functional debugging and the qualification phases. Additionally, a power supply circuit with a
correct layout needs smaller EMI filters or less filter stages which allows consistent cost
saving.
attention by the design engineers like any other design phase. Even if it the layout phase
sometimes looks time-consuming, a good layout does indeed save time during the
functional debugging and the qualification phases. Additionally, a power supply circuit with a
correct layout needs smaller EMI filters or less filter stages which allows consistent cost
saving.
Converters using the L6563H do not require any special or specific layout rule, just the
general layout rules for any power converter have to be applied carefully. Basic rules are
listed here below. They can be used for other PFC circuits having any power level, working
either in transition mode or with a fixed-off time control.
general layout rules for any power converter have to be applied carefully. Basic rules are
listed here below. They can be used for other PFC circuits having any power level, working
either in transition mode or with a fixed-off time control.
1.
Keep power and signal RTN separated. Connect the return pins of components
carrying high current such as the input filter, sense resistors, or the output capacitor as
close as possible. This point is the RTN star point. A downstream converter will have to
be connected to this return point.
carrying high current such as the input filter, sense resistors, or the output capacitor as
close as possible. This point is the RTN star point. A downstream converter will have to
be connected to this return point.
2.
Minimize the length of the traces relevant to the boost inductor, MOSFET drain, boost
rectifier and output capacitor.
rectifier and output capacitor.
3.
Keep signal components as close as possible to each L6563H relevant pin. Specifically,
keep the tracks relevant to the pin #1 (INV) net as short as possible. Components and
traces relevant to the error amplifier have to be placed far from traces and connections
carrying signals with high dV/dt like the MOSFET drain. For high-power converters or
very compact PCB layouts, a 10 nF capacitor connected to pin #8 (PWM_LATCH) and
pin #14 (GND) might be required to decrease the noise picked up by this pin while it is
in its high impedance status.
keep the tracks relevant to the pin #1 (INV) net as short as possible. Components and
traces relevant to the error amplifier have to be placed far from traces and connections
carrying signals with high dV/dt like the MOSFET drain. For high-power converters or
very compact PCB layouts, a 10 nF capacitor connected to pin #8 (PWM_LATCH) and
pin #14 (GND) might be required to decrease the noise picked up by this pin while it is
in its high impedance status.
4.
Please connect heatsinks to power GND.
5.
Add an external shield to the boost inductor and connect it to power GND.
6.
Please connect the RTN of signal components including the feedback, PFC_OK and
MULT dividers close to the L6563H pin #14 (GND).
MULT dividers close to the L6563H pin #14 (GND).
7.
Connect a ceramic capacitor (100÷470 nF) to pin #16 (Vcc) and pin #14 (GND), close
to the L6563H. Connect this point to the RTN star point (see rule
to the L6563H. Connect this point to the RTN star point (see rule