Intel 1.40 GHz RH80532NC017256 Ficha De Dados
Códigos do produto
RH80532NC017256
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet
41
Table 24. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
Symbol Parameter
Min
Max
Unit
Notes
V
IL15
Input Low Voltage, 1.5 V CMOS
–0.15
V
CMOSREFmin
– 300 mV
V
V
IL18
Input Low Voltage, 1.8 V CMOS
–0.36
0.36
V
Notes 1, 2
V
IH15
Input High Voltage, 1.5 V CMOS
V
CMOSREFmax
+
250 mV
2.0
V
Note 10
V
IH15PICD
Input High Voltage, 1.5 V PICD[1:0]
V
CMOSREFmax
+
200 mV
2.0
V
Note 11
V
IH18
Input High Voltage, 1.8 V CMOS
1.44
2.0
V
Notes 1, 2
V
OH15
Output High Voltage, 1.5 V CMOS
N/A
1.615
V
All outputs are Open-drain
V
OH33
Output High Voltage, 3.3 V signals
2.0
3.465
V
3.3V + 5%
V
OL33
Output Low Voltage, 3.3 V signals
0.8
V
V
OL
Output Low Voltage
0.3
V
Note 8
V
CMOSREF
CMOSREF Voltage
0.90
1.10
V
Note 4
V
CLKREF
CLKREF Voltage
1.187
1.312
V
Note 9
V
ILVTTPWR
Input Low Voltage, VTTPWRGD
0.4
V
Note 7
V
IHVTTPWR
Input High Voltage, VTTPWRGD
1.0
V
Note 7
R
ON
30
Ω
Note 3
I
OL
Output Low Current
10
mA
Note 6
I
L
Leakage Current for Inputs, Outputs
and I/Os
and I/Os
±100
µA
Note 5
NOTES:
1. Parameter applies to the PWRGOOD signal only.
2. V
2. V
Ilx,min
and V
Ihx,max
only apply when BCLK, BCLK# and PICCLK are stopped. PICCLK should be stopped in the
low state. See Table 33 and Table 34 for DC levels when BCLK and BCLK# are stopped.
3. Measured at 9 mA.
4. V
4. V
CMOSREF
should be created from a stable 1.5-V supply using a voltage divider. It must track the voltage supply
to maintain noise immunity. The same 1.5-V supply should be used to power the chipset CMOS I/O buffers that
drive these signals.
drive these signals.
5. (0
≤
VIN/OUT
≤ V
Ihx,max
).
6. Specified as the minimum amount of current that the output buffer must be able to sink. However, V
OL,max
cannot
be guaranteed if this specification is exceeded.
7. Parameter applies to VTTPWRGD signal only.
8. Applies to non-AGTL signals except BCLK, PWRGOOD, PICCLK, BSEL[1:0], VID[4:0].
9. ±5% DC tolerance. CLKREF must be generated from the 2.5-V supply used to generate the BCLK signal. AC
8. Applies to non-AGTL signals except BCLK, PWRGOOD, PICCLK, BSEL[1:0], VID[4:0].
9. ±5% DC tolerance. CLKREF must be generated from the 2.5-V supply used to generate the BCLK signal. AC
Tolerance must be less than –40 dB @ 1 MHz.
10. Applies to all TAP and CMOS signals (not to APIC signals).
11. Applies to PICD[1:0].
11. Applies to PICD[1:0].
3.6 AC
Specifications
3.6.1
System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC
Specifications
Specifications
All system bus AC specifications for the AGTL signal group are relative to the crossing point of the
rising edge of the BCLK input and falling edge of the BCLK# input. All AGTL timings are referenced to
V
rising edge of the BCLK input and falling edge of the BCLK# input. All AGTL timings are referenced to
V
REF
for both “0” and “1” logic levels unless otherwise specified. All APIC, TAP, CMOS, and Open-
drain signals except PWRGOOD are referenced to 1.0 V. All minimum and maximum specifications are
at points within the power supply ranges shown in Table 12 through Table 21 and junction temperatures
at points within the power supply ranges shown in Table 12 through Table 21 and junction temperatures