Intel U1300 LE80538UE0042M Ficha De Dados

Specification Update  

 49

 

If an asynchronous machine check occurs during an interrupt, call through gate, FAR 

RET or IRET and in the presence of certain internal conditions, ESP may be corrupted. 

Implication:  If the MCE (Machine Check Exception) handler is called without a stack switch, then a 

triple fault will occur due to the corrupted stack pointer, resulting in a processor 

shutdown. If the MCE is called with a stack switch, e.g., when the CPL (Current 

Privilege Level) was changed or when going through an interrupt task gate, then the 

corrupted ESP will be saved on the new stack or in the TSS (Task State Segment), 

and will not be used. 

Workaround: Use an interrupt task gate for the machine check handler. 

For the steppings affected, see the 

Summary Tables of Changes

. 

According to IA-32 Intel Architecture Software Developer's Manual, Volume 3A 

"Methods of Caching Available", WP (Write Protected) stores should drain the WC 

(Write Combining) buffers in the same way as UC (Uncacheable) memory type stores 

do. Due to this erratum, WP stores may not drain the WC buffers. 

Implication:  Memory ordering may be violated between WC and WP stores. 

Workaround: None identified 

Status: 

For the steppings affected, see the 

Summary Tables of Changes.

 

Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) 

counts transitions from x87 Floating Point (FP) to MMX™ technology instructions. Due 

to this erratum, if only a small number of MMX technology instructions (including 

EMMS) are executed immediately after the last FP instruction, a FP to MMX technology 

transition may not be counted. 

Implication:  The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be 

lower than expected. The degree of undercounting is dependent on the occurrences of 

the erratum condition while the counter is active. Intel has not observed this erratum 

with any commercially-available software. 

Workaround:  None identified. 

For the steppings affected, see the 

Summary Tables of Changes. 

Under certain conditions, as described in the Software Developers Manual section 

"Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family 

Processors", the processor may perform REP MOVS or REP STOS as write combining