Intel 4 519K HH80547PE0831MN Ficha De Dados

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The Sleep state is a very low power state in which the processor maintains its context, maintains 
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be 
entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state 
upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is 
in the Stop Grant state. SLP# assertions while the processor is not in the Stop Grant state is out of 
specification and may result in erroneous processor operation. 

Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will 
cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching 
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) 
are allowed on the FSB while the processor is in Sleep state. Any transition on an input signal 
before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in 
the RESET# pin specification, then the processor will reset itself, ignoring the transition through 
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# 
and STPCLK# signals should be de-asserted immediately after RESET# is asserted to ensure the 
processor correctly executes the reset sequence.

Once in the Sleep state, the SLP# pin must be de-asserted if another asynchronous FSB event needs 
to occur. The SLP# pin has a minimum assertion of one BCLK period.

When the processor is in the Sleep state, it will not respond to interrupts or snoop transactions.

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