Intel 4 HT 651 80552PG0962M2M Ficha De Dados
Códigos do produto
80552PG0962M2M
Land Listing and Signal Descriptions
66
Datasheet
BR0#
Input/
Output
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
signal is sampled to determine the agent ID = 0.
This signal does not have on-die termination and must be
terminated.
processor to request the bus. During power-on configuration this
signal is sampled to determine the agent ID = 0.
This signal does not have on-die termination and must be
terminated.
BSEL[2:0]
Output
The BCLK[1:0] frequency select signals BSEL[2:0] are used to
select the processor input clock frequency.
select the processor input clock frequency.
possible combinations of the signals and the frequency associated
with each combination. The required frequency is determined by
the processor, chipset and clock synthesizer. All agents must
operate at the same frequency. For more information about these
signals, including termination recommendations, refer to
with each combination. The required frequency is determined by
the processor, chipset and clock synthesizer. All agents must
operate at the same frequency. For more information about these
signals, including termination recommendations, refer to
COMP[5:4,1:0]
Analog
COMP[1:0] must be terminated to V
SS
on the system board using
precision resistors. COMP[5:4] must be terminated to V
TT
on the
system board using precision resistors.
D[63:0]#
Input/
Output
D[63:0]# (Data) are the data signals. These signals provide a 64-
bit data path between the processor FSB agents, and must connect
the appropriate pins/lands on all such agents. The data driver
asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of
16 data signals correspond to a pair of one DSTBP# and one
DSTBN#. The following table shows the grouping of data signals to
data strobes and DBI#.
bit data path between the processor FSB agents, and must connect
the appropriate pins/lands on all such agents. The data driver
asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of
16 data signals correspond to a pair of one DSTBP# and one
DSTBN#. The following table shows the grouping of data signals to
data strobes and DBI#.
Furthermore, the DBI# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
Quad-Pumped Signal Groups
Data Group
DSTBN#/
DSTBP#
DBI#
D[15:0]#
0
0
D[31:16]#
1
1
D[47:32]#
2
2
D[63:48]#
3
3