Intel ULV 383 LE80536VC0011M Ficha De Dados
Códigos do produto
LE80536VC0011M
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet
25
at 1.10V (for 500 MHz, 600 MHz)
at 1.15V (for 600 MHz)
at 1.35V (for 400A MHz, 500 MHz, 600 MHz)
at 1.60V (for 450 MHz, 500 MHz, 550 MHz, 600
MHz, 650 MHz)
at 1.60V (for 700 MHz, 750 MHz)
at 1.60V (for 800 MHz, 850 MHz)
at 1.70V (for 900 MHz)
at 1.15V (for 600 MHz)
at 1.35V (for 400A MHz, 500 MHz, 600 MHz)
at 1.60V (for 450 MHz, 500 MHz, 550 MHz, 600
MHz, 650 MHz)
at 1.60V (for 700 MHz, 750 MHz)
at 1.60V (for 800 MHz, 850 MHz)
at 1.70V (for 900 MHz)
1.3
1.4
1.5
1.9
3.0
3.29
3.46
1.4
1.5
1.9
3.0
3.29
3.46
A
A
A
A
A
A
A
A
A
A
A
A
A
I
CC,DSLP
Processor Deep Sleep Leakage current
at 1.10V (for 500 MHz, 600 MHz)
at 1.15V (for 600 MHz)
at 1.35V (for 400A MHz, 500 MHz, 600 MHz)
at 1.60V (for 450 MHz, 500 MHz, 550 MHz, 600
MHz, 650 MHz)
at 1.60V (for 700 MHz, 750 MHz)
at 1.60V (for 800 MHz, 850 MHz)
at 1.70V (for 900 MHz)
at 1.15V (for 600 MHz)
at 1.35V (for 400A MHz, 500 MHz, 600 MHz)
at 1.60V (for 450 MHz, 500 MHz, 550 MHz, 600
MHz, 650 MHz)
at 1.60V (for 700 MHz, 750 MHz)
at 1.60V (for 800 MHz, 850 MHz)
at 1.70V (for 900 MHz)
1.1
1.3
1.2
1.6
2.5
3.0
3.0
A
A
A
A
A
A
A
Note 4
dI
CC
/dt V
CC
power supply current slew rate
1400 A/
µ
s Notes 5, 6
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Static voltage regulation includes: DC output initial voltage set point adjust, output ripple and noise, output
load ranges specified in Table 9 above, temperature, and warm up.
load ranges specified in Table 9 above, temperature, and warm up.
3.
I
CCT
is the current supply for the system bus buffers, including the on-die termination.
4.
I
CCx,max
specifications are specified at V
CC,DC max
, V
CCT,max
, and 100°C and under maximum signal
loading conditions.
5.
Based on simulations and averaged over the duration of any change in current. Use to compute the
maximum inductance and reaction time of the voltage regulator. This parameter is not tested.
maximum inductance and reaction time of the voltage regulator. This parameter is not tested.
6.
Maximum values specified by design/characterization at nominal V
CC
and V
CCT
.
7.
V
CCx
must be within this range under all operating conditions, including maximum current transients. V
CCx
must return to within the static voltage specification, V
CCx,DC
, within 100
µ
s after a transient event. The
average of V
CCx
over time must not exceed 1.65V, as an arbitrarily large time span may be used for this
average.
8.
Voltages are measured at the processor package pin for the Micro-PGA2 part and at the package ball on
the BGA2 part.
the BGA2 part.
The signals on the mobile Intel Celeron processor system bus are included in the GTL+ signal
group. These signals are specified to be terminated to V
group. These signals are specified to be terminated to V
CCT
. The DC specifications for these
signals are listed in Table 10 and the termination and reference voltage specifications for these
signals are listed in Table 11. The mobile Intel Celeron processor requires external termination
and a V
signals are listed in Table 11. The mobile Intel Celeron processor requires external termination
and a V
REF
. Refer to the Mobile Pentium
®
III Processor GTL+ System Bus Layout Guideline for
full details of system V
CCT
and V
REF
requirements. The CMOS, Open-drain, and TAP signals are
designed to interface at 1.5V levels to allow connection to other devices. BCLK and PICCLK are
designed to receive a 2.5-V clock signal. The DC specifications for these signals are listed Table
12.
designed to receive a 2.5-V clock signal. The DC specifications for these signals are listed Table
12.
Table 10. GTL+ Signal Group DC Specifications
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100
mV or 1.60V ±115; V
CCT
= 1.50V ±115 mV
Symbol Parameter
Min Max Unit
Notes
V
OH
Output High Voltage
—
—
V
See V
CCT,max
in Table 11
R
ON
Output Low Drive Strength
16.67
Ω
I
L
Leakage Current for Inputs, Outputs and I/Os
±100
µ
A
Note 1