Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet 1 of 2

Document Number: 327405

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001

13

DDR3

Third-generation Double Data Rate SDRAM memory technology

DMA

Direct Memory Access

DMI

Direct Media Interface

DTS

Digital Thermal Sensor

ECC

Error Correction Code

Enhanced Intel SpeedStep

®

 

Technology

Technology that provides power management capabilities to laptops.

Execute Disable Bit

The Execute Disable bit allows memory to be marked as executable or non-

executable, when combined with a supporting operating system. If code 

attempts to run in non-executable memory the processor raises an error to 

the operating system. This feature can prevent some classes of viruses or 

worms that exploit buffer overrun vulnerabilities and can thus help improve 

the overall security of the system. See the Intel

Architectures Software Developer's Manuals for more detailed information.

HFM

High Frequency Mode

IMC

Integrated Memory Controller

Intel

®

 64 Technology

64-bit memory extensions to the IA-32 architecture

Intel

®

 TXT

Intel

®

 Trusted Execution Technology is a versatile set of hardware 

extensions to Intel® processors and chipsets that enhance the digital office 

platform with security capabilities such as measured launch and protected 

execution. Intel® Trusted Execution Technology provides hardware-based 

mechanisms that help protect against software-based attacks and protects 

the confidentiality and integrity of data stored or created on the client PC. 

Intel

®

 VT-d

Intel

®

 Virtualization Technology (Intel

®

 VT) for Directed I/O. Intel

®

 VT-d is 

a hardware assist, under system software (Virtual Machine Manager or OS) 

control, for enabling I/O device virtualization. Intel VT-d also brings robust 

security by providing protection from errant DMAs by using DMA 

remapping, a key feature of Intel VT-d.

Intel

®

 Virtualization Technology 

Processor virtualization which when used in conjunction with Virtual 

Machine Monitor software enables multiple, robust independent software 

environments inside a single platform.

IOV

I/O Virtualization

LFM

Low Frequency Mode

NCTF

Non-Critical to Function. NCTF locations are typically redundant ground or 

non-critical reserved, so the loss of the solder joint continuity at end of life 

conditions will not affect the overall product functionality.

Nehalem

Intel’s 45-nm processor design, follow-on to the 45-nm Penryn design.

ODT

On-Die termination

PCH

Platform Controller Hub. The new, 2009 chipset with centralized platform 

capabilities including the main I/O interfaces along with power 

management, manageability, security and storage features.

PCLMULQDQ

Single Instruction Multiple Data (SIMD) instruction that computes the 128-

bit carry-less multiplication of two, 64-bit operands without generating and 

propagating carries.

PECI

Platform Environment Control Interface.

Processor

The 64-bit, single-core or multi-core component (package).

Processor Core

The term “processor core” refers to Si die itself which can contain multiple 

execution cores. Each execution core has an instruction cache, data cache, 

and 256-KB L2 cache. All execution cores share the L3 cache.