Intel E3-1105C AV8062701048800 Ficha De Dados

Códigos do produto

AV8062701048800

Interfaces

Intel

Xeon

and Intel

Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

001

3.0

Interfaces

This chapter describes the interfaces supported by the processor.

3.1

System Memory Interface

3.1.1

System Memory Configurations Supported

The Integrated Memory Controller (IMC) of the processor supports DDR3 protocols with

two independent, 72-bit wide channels. These two memory channels are capable of

running speeds up to 1600MT/s. Each channel consists of 64 data and 8 ECC bits. In

the dual-channel configuration, it supports DIMMs on both channels, or DIMMs on one

channel and memory down configuration on the other channel, or memory down

configuration on both channels. The processor supports up to two DIMMs per channel.

Note:

Very Low Profile (VLP) UDIMMs are supported wherever UDIMMs are supported.

However, VLP UDIMMs have not been fully validated.

Note:

Mixing of ECC and Non-ECC DIMMs is not supported.