Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

30

Document Number: 327405

-

001

The processor has four PCI Express* controllers that can be independently configured 

to either Gen 1 or Gen 2, allowing operation at both 2.5 GT/s (Giga-Transfers per 

second) and 5.0 GT/s data rates. These four PCIe* devices operate simultaneously 

which are configurable in the following combinations:

• 1 x16 PCI Express* Port with 1 x4 PCI Express Port
• 2 x8 PCI Express* Ports with 1 x4 PCI Express* Port
• 1 x8 PCI Express* Ports with 3 x4 PCI Express* Ports

The 1 Core SKU (see 

) only supports 16 PCI 

Express* Ports, and a maximum of three PCIe* devices. These three PCIe* devices 

operate simultaneously which are configurable in the following combinations:

• 1 x16 PCI Express* Port 
• 2 x8 PCI Express* Ports 
• 1 x8 PCI Express* Port with 2 x4 PCI Express* Ports
• 3 x4 PCI Express* Ports

Compatibility with the PCI addressing model is maintained to ensure that all existing 

applications and drivers operate unchanged. 

The PCI Express* configuration uses standard mechanisms as defined in the PCI 

Plug-and-Play specification. The initial recovered clock speed of 1.25 GHz results in 

2.5 Gb/s/direction which provides a 250 MB/s communications channel in each 

direction (500 MB/s total). That is nearly twice the data rate of classic PCI. The fact 

that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would 

imply 300 MB/s. The external ports support Gen2 speed as well. At 5.0 GT/s, Gen 2 

operation results in double the bandwidth per lane as compared to Gen 1 operation. 

When operating with two PCIe* controllers, each controller can be operating at either 

2.5 GT/s or 5.0 GT/s.

The PCI Express* architecture is specified in three layers: Transaction Layer, Data Link 

Layer, and Physical Layer. The partitioning in the component is not necessarily along 

these same boundaries. See 

 for the PCI Express* Layering Diagram.