Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

92

Document Number: 327405

-

001

Due to the voltage levels supported by other components in the Test Access Port (TAP) 

logic, Intel recommends the processor be first in the TAP chain, followed by any other 

components within the system. A translation buffer should be used to connect to the 

rest of the chain unless one of the other components is capable of accepting an input of 

the appropriate voltage. Two copies of each signal may be required with each driving a 

different voltage level. 

The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE 1149.6-

2003 standards. Some small portion of the I/O pins may support only one of these 

standards.

Some of the I/O pins may support only one of these standards.

Environmental storage condition limits define the temperature and relative humidity to 

which the device is exposed to while being stored in a moisture barrier bag. The 

specified storage conditions are for component level prior to board attach.

 specifies absolute maximum and minimum storage temperature limits which 

represent the maximum or minimum device condition beyond which damage, latent or 

otherwise, may occur. The table also specifies sustained storage temperature, relative 

humidity, and time-duration limits. These limits specify the maximum or minimum 

device storage conditions for a sustained period of time. Failure to adhere to the 

following specifications can affect long term reliability of the processor.

Differential

PCI Express* Input

PCIE_RX[15:0], PCIE_RX#[15:0]
PE_RX[3:0], PE_RX#[3:0]

Differential

PCI Express* Output

PCIE_TX[15:0], PCIE_TX#[15:0]
PE_TX[3:0], PE_TX#[3:0]

Single Ended

Analog Input

PCIE_ICOMP0, PCIE_ICOMPI, 

PCIE_RCOMP0

Differential

DMI Input

DMI_RX[3:0], DMI_RX#[3:0]

Differential

DMI Output

DMI_TX[3:0], DMI_TX#[3:0]

PROC_SELECT#,
VCCSA_VID[0],
SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

1.

See 

 for signal description details.

2.

SA and SB see DDR3 Channel A and DDR3 Channel B.

3.

All Control Sideband Asynchronous signals are required to be asserted/deasserted for at least 10 

BCLKs with a maximum Trise/Tfall of 6 ns for the processor to recognize the proper signal state. See 

 and 

 for the DC and AC specifications.

4.

The maximum rise/fall time of UNCOREPWRGOOD is 20 ns.