Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

95

Ripple

Ripple Tolerance

PS0 & Icc > 
TDC+30%

+/- 15

mV

8, 10

PS0 & Icc <= 
TDC+30%

+/- 10

PS1

+/- 13

PS2

- 7.5/+18.5

PS3

- 7.5/+27.5

VOvS_Max

Max Overshoot Voltage

50

mV

tOvS_Max

Max Overshoot Time 

Duration

10

uS

VR Step

VID resolution

5

mV

SLOPE

LL

Processor Loadline Slope

-1.9
-1.9
-2.9
-2.9
-2.9

m

Ω

1.

These specifications have been updated with characterized data from silicon measurements.

2.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing 

and cannot be altered. Individual maximum SVID values are calibrated during manufacturing such that two processors 

at the same frequency may have different settings within the SVID range. This differs from the SVID employed by the 

processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep 

Technology, or Low Power States). 

3.

The voltage specification requirements are measured across V

CC_SENSE

 and V

SS_SENSE

 balls at the socket with a 100-MHz 

bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of 

ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the 

oscilloscope probe. 

4.

See the  Platform Design Guide for the minimum, typical, and maximum V

CC

 allowed for a given current. The processor 

should not be subjected to any V

CC

 and I

CC

 combination wherein V

CC

 exceeds V

CC_MAX

 for a given current.

5.

Processor core VR to be designed to electrically support this current

6.

Processor core VR to be designed to thermally support this current indefinitely.

7.

Measured at V

CC_SENSE

 and V

SS_SENSE 

processor pins.

8.

Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are violated

9.

Long term reliability cannot be assured in conditions above or below Max/Min functional limits.

10.

PSx refers to the voltage regulator power state as set by the SVID protocol. 

11.

Step is done in 150 ns

12.

Slew time for any transient step size.

13.

Simulated at platform processor pads. This parameter is not tested.