Intel i5-4200H CL8064701470601 Ficha De Dados

Test Point

RSVD_TP

Other

SKTOCC#, PROC_DETECT#3 

Differential

PCI Express Input

PEG_RXP[15:0], PEG_RXN[15:0]

Differential

PCI Express Output

PEG_TXP[15:0], PEG_TXN[15:0]

Single ended

Analog Input

PEG_RCOMP

Differential

eDP Output

eDP_TXP[3:0], eDP_TXN[3:0]

Single ended

Asynchronous

CMOS Input

eDP_HPD

Single ended

Analog Input/

Output

eDP_RCOMP

Differential

DMI Input

DMI_RXP[3:0], DMI_RXN[3:0]

Differential

DMI Output

DMI_TXP[3:0], DMI_TXN[3:0]

Differential

DDI Output

DDIB_TXP[3:0], DDIB_TXN[3:0], DDIC_TXP[3:0],

DDIC_TXN[3:0], DDID_TXP[3:0], DDID_TXN[3:0]

Single ended

CMOS Input

FDI_CSYNC

Single ended

Asynchronous

CMOS Input

DISP_INT

Differential

FDI Output

FDI_TXP[1:0], FDI_TXN[1:0]

Notes: 1. See 

 on page 83 for signal description details.

2. SA and SB refer to DDR3L/DDR3L-RS Channel A and DDR3L/DDR3L-RS Channel B.
3. These signals only apply to BGA packages.

Due to the voltage levels supported by other components in the Test Access Port

(TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any

other components within the system. A translation buffer should be used to connect to

the rest of the chain unless one of the other components is capable of accepting an

input of the appropriate voltage. Two copies of each signal may be required with each

driving a different voltage level.

The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE

1149.6-2003 standards. A few of the I/O pins may support only one of those

standards.

The processor DC specifications in this section are defined at the processor pins,

 on page 83 for the processor pin

listings and signal definitions.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

100

Order No.: 328901-007