Intel i5-4200H CL8064701470601 Ficha De Dados

LFP

Local Flat Panel

LPDDR3

Low-Power Third-generation Double Data Rate SDRAM memory technology

MCP

Multi-Chip Package

MFM

Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and

can be read from MSR CEh [55:48].

MLE

Measured Launched Environment

MLC

Mid-Level Cache

MSI

Message Signaled Interrupt

MSL

Moisture Sensitive Labeling

MSR

Model Specific Registers

NCTF

Non-Critical to Function. NCTF locations are typically redundant ground or non-critical

reserved, so the loss of the solder joint continuity at end of life conditions will not

affect the overall product functionality.

ODT

On-Die Termination

OLTM

Open Loop Thermal Management

PCG

Platform Compatibility Guide (PCG) (previously known as FMB) provides a design

target for meeting all planned processor frequency requirements.

PCH

Platform Controller Hub. The chipset with centralized platform capabilities including

the main I/O interfaces along with display connectivity, audio features, power

management, manageability, security, and storage features.

PECI

The Platform Environment Control Interface (PECI) is a one-wire interface that

provides a communication channel between Intel processor and chipset components

to external monitoring devices.

Ψ

 ca

Case-to-ambient thermal characterization parameter (psi). A measure of thermal

solution performance using total package power. Defined as (T

CASE

 - T

LA

 ) / Total

Package Power. The heat source should always be specified for Y measurements.

PEG

PCI Express* Graphics. External Graphics using PCI Express* Architecture. It is a

high-speed serial interface where configuration is software compatible with the

existing PCI specifications.

PL1, PL2

Power Limit 1 and Power Limit 2

PPD

Pre-charge Power-down

Processor

The 64-bit multi-core component (package)

Processor Core

The term “processor core” refers to Si die itself, which can contain multiple execution

cores. Each execution core has an instruction cache, data cache, and 256-KB L2

cache. All execution cores share the L3 cache.

Processor Graphics

Intel Processor Graphics

Rank

A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These

devices are usually, but not always, mounted on a single side of a SO-DIMM.

SCI

System Control Interrupt. SCI is used in the ACPI protocol.

SF

Strips and Fans

SMM

System Management Mode

SMX

Safer Mode Extensions

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 328901-007

15