Intel i5-4200H CL8064701470601 Ficha De Dados
Códigos do produto
CL8064701470601
•
Standard 1Gb, 2Gb, and 4Gb technologies and addressing are supported for x8
devices. There is no support for memory modules with different technologies or
capacities on opposite sides of the same memory module. If one side of a memory
module is populated, the other side is either identical or empty.
Table 4.
Supported SO-DIMM Module Configurations
Raw Card
Version
DIMM
Capacity
DRAM
Organization
# of DRAM
Devices
# of Row/Col
Address Bits
# of Banks
Inside DRAM
Page Size
B
1 GB
128 M x 8
8
14/10
8
8K
2 GB
256 M x 8
8
15/10
8
8K
4 GB
512 M x 8
8
16/10
8
8K
F
2 GB
128 M x 8
16
14/10
8
8K
4 GB
256 M x 8
16
15/10
8
8K
8 GB
512 M x 8
16
16/10
8
8K
Table 5.
Supported Maximum Memory Size Per DIMM
Platform
Package
Memory DDR3L
(note 1)
DDR3L-RS
(note 2)
Maximim Size
per DIMM
[GB]
Maximum Size Per Configuration [GB]
1 Ch
1 DPC
1 Ch
2 DPC
(note 4)
2 Ch
1 DPC
2 Ch
2 DPC
Mobile M-
Processor /
Mobile H-
Processor
rPGA, BGA
SODIMM RC B
(1Rx8)
(note 3)
(note 3)
4
4
8
8
16
SODIMM RC F
(2Rx8)
(note 3, 5)
(note 3, 5)
8
8
16
16
32
Notes: 1. The maximum High Density memory capacity is achieved using 4 Gigabit memory technology devices (1 and 2
Gigabit devices are also supported).
2. DDR3L-RS is supported as a POR memory configuration as Intel expects these parts to be electrically and software
identical to DDR3L. Actual validation checkout would depend on parts and vendor availability. PMO list for actual
vendors and parts validated is available at
3. Raw Cards x16 SO-DIMM modules are not supported.
4. 1 DPC on 4SODIMM Board (2 total memory DIMMs populated) is supported.
5. Memory Down using DDR3L 2Rx8 and 1Rx32 (DDP) configurations are supported using a white paper design
4. 1 DPC on 4SODIMM Board (2 total memory DIMMs populated) is supported.
5. Memory Down using DDR3L 2Rx8 and 1Rx32 (DDP) configurations are supported using a white paper design
guidance.
System Memory Timing Support
The IMC supports the following DDR3L/DDR3L-RS Speed Bin, CAS Write Latency
(CWL), and command signal mode timings on the main memory interface:
•
•
tCL = CAS Latency
•
tRCD = Activate Command to READ or WRITE Command delay
•
tRP = PRECHARGE Command Period
•
CWL = CAS Write Latency
•
Command Signal modes = 1N indicates a new command may be issued every
clock and 2N indicates a new command may be issued every 2 clocks. Command
launch mode programming depends on the transfer rate and memory
configuration.
2.1.2
Interfaces—Processor
Mobile 4th Generation Intel
®
Core
™
Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and Mobile Intel
®
Celeron
®
Processor Family
July 2014
Datasheet – Volume 1 of 2
Order No.: 328901-007
19