Intel i5-4200H CL8064701470601 Ficha De Dados
Códigos do produto
CL8064701470601
•
Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
— DMI -> PCI Express* Port 0
— DMI -> PCI Express* Port 1
— PCI Express* Port 0 -> DMI
— PCI Express* Port 1 -> DMI
— DMI -> PCI Express* Port 0
— DMI -> PCI Express* Port 1
— PCI Express* Port 0 -> DMI
— PCI Express* Port 1 -> DMI
•
64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
•
64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
•
Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status.
•
PCI Express* reference clock is 100-MHz differential clock.
•
Power Management Event (PME) functions.
•
Dynamic width capability.
•
Message Signaled Interrupt (MSI and MSI-X) messages.
•
Polarity inversion
•
Dynamic lane numbering reversal as defined by the PCI Express Base
Specification.
•
Static lane numbering reversal. Does not support dynamic lane reversal, as
defined (optional) by the PCI Express Base Specification.
•
Supports Half Swing “low-power/low-voltage” mode.
Note:
The processor does not support PCI Express* Hot-Plug.
PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-
and-Play specification. The processor PCI Express* ports support Gen 3. At 8 GT/s,
Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2
operation. The 16 lanes PEG can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s.
Gen 3 PCI Express* uses a 128b/130b encoding that is about 23% more efficient than
the 8b/10b encoding used in Gen 1 and Gen 2.
The PCI Express* architecture is specified in three layers – Transaction Layer, Data
Link Layer, and Physical Layer. See the PCI Express Base Specification 3.0 for details
of PCI Express* architecture.
PCI Express* Configuration Mechanism
The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
2.2.2
2.2.3
Processor—Interfaces
Mobile 4th Generation Intel
®
Core
™
Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and Mobile Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2
July 2014
24
Order No.: 328901-007