Intel i5-4200H CL8064701470601 Ficha De Dados

— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt

processor addressability up to 4G–1 processors in physical destination mode.

A processor implementation of x2APIC architecture can support fewer than 32-

bits in a software transparent fashion.

— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical

x2APIC ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit

logical ID within the cluster. Consequently, ((2^20) – 16) processors can be

addressed in logical destination mode. Processor implementations can support

fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a

software agnostic fashion.

•

More efficient MSR interface to access APIC registers:
— To enhance inter-processor and self-directed interrupt delivery as well as the

ability to virtualize the local APIC, the APIC register set can be accessed only

through MSR-based interfaces in x2APIC mode. The Memory Mapped IO

(MMIO) interface used by xAPIC is not supported in x2APIC mode.

•

The semantics for accessing APIC registers have been revised to simplify the

programming of frequently-used APIC registers by system software. Specifically,

the software semantics for using the Interrupt Command Register (ICR) and End

Of Interrupt (EOI) registers have been modified to allow for more efficient delivery

and dispatching of interrupts.

•

The x2APIC extensions are made available to system software by enabling the

local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a

new operating system and a new BIOS are both needed, with special support for

x2APIC mode.

•

The x2APIC architecture provides backward compatibility to the xAPIC architecture

and forward extendible for future Intel platform innovations.

Intel x2APIC Technology may not be available on all SKUs.

For more information, see the Intel

 64 Architecture x2APIC Specification at 

.

The processor includes enhanced power-performance technology that routes

interrupts to threads or cores based on their sleep states. As an example, for energy

savings, it routes the interrupt to the active cores without waking the deep idle cores.

For performance, it routes the interrupt to the idle (C1) cores without interrupting the

already heavily loaded cores. This enhancement is mostly beneficial for high-interrupt

scenarios like Gigabit LAN, WLAN peripherals, and so on.

The Execute Disable Bit allows memory to be marked as executable when combined

with a supporting operating system. If code attempts to run in non-executable

memory, the processor raises an error to the operating system. This feature can

prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities

and can thus help improve the overall security of the system. See the Intel

IA-32 Architectures Software Developer's Manuals for more detailed information.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 328901-007

49