Intel i5-4200H CL8064701470601 Ficha De Dados

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CL8064701470601
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Note: 
Package C6 state is the deepest C-state supported on discrete graphics systems with
PCI Express Graphics (PEG).
Package C7 state is the deepest C-state supported on integrated graphics systems (or
switchable graphics systems during integrated graphics mode). However, in most
configurations, package C6 will be more energy efficient than package C7 state. As a
result, package C7 state residency is expected to be very low or zero in most
scenarios where the display is enabled. Logic internal to the processor will determine
whether package C6 or package C7 state is the most efficient. There is no need to
make changes in BIOS or system software to prioritize package C6 state over package
C7 state.
Dynamic L3 Cache Sizing
When all cores request C7 or deeper C-state, internal heuristics is dynamically flushes
the L3 cache. Once the cores enter a deep C-state, depending on their MWAIT
substate request, the L3 cache is either gradually flushed N-ways at a time or flushed
all at once. Upon the cores exiting to C0, the L3 cache is gradually expanded based on
internal heuristics.
Package C-States and Display Resolutions
The integrated graphics engine has the frame buffer located in system memory. When
the display is updated, the graphics engine fetches display data from system memory.
Different screen resolutions and refresh rates have different memory latency
requirements. These requirements may limit the deepest Package C-state the
processor can enter. Other elements that may affect the deepest Package C-state
available are the following:
Display is on or off
Single or multiple displays
Native or non-native resolution
Panel Self Refresh (PSR) technology
Note: 
Display resolution is not the only factor influencing the deepest Package C-state the
processor can get into. Device latencies, interrupt response latencies, and core C-
states are among other factors that influence the final package C-state the processor
can enter.
The following table lists display resolutions and deepest available package C-State.
The display resolutions are examples using common values for blanking and pixel
rate. Actual results will vary. The table shows the deepest possible Package C-state.
System workload, system idle, and AC or DC power also affect the deepest possible
Package C-state.
Table 20.
Deepest Package C-State Available – M-Processor Line
Panel Self Refresh
(PSR)
Number of Displays 
1
Native Resolution 
2
Deepest Available
Package C-State
Disabled
Single
800x600 60 Hz
PC6
Disabled
Single
1024x768 60 Hz
PC6
Disabled
Single
1280x1024 60 Hz
PC6
continued...   
4.2.6  
Power Management—Processor
Mobile 4th Generation Intel
®
 Core
 Processor Family, Mobile Intel
®
 Pentium
®
 Processor Family, and Mobile Intel
®
 Celeron
®
Processor Family
July 2014
Datasheet – Volume 1 of 2
Order No.: 328901-007
61