Intel i5-4200H CL8064701470601 Ficha De Dados

SB_BS[2:0]

Bank Select: These signals define which banks are selected

within each SDRAM rank.

O

DDR3L

/DDR3L-RS

SB_WE#

Write Enable Control Signal: This signal is used with

SB_RAS# and SB_CAS# (along with SB_CS#) to define the

SDRAM Commands.

O

DDR3L

/DDR3L-RS

SB_RAS#

RAS Control Signal: This signal is used with SB_CAS# and

SB_WE# (along with SB_CS#) to define the SRAM Commands.

O

DDR3L

/DDR3L-RS

SB_CAS#

CAS Control Signal: This signal is used with SB_RAS# and

SB_WE# (along with SB_CS#) to define the SRAM Commands.

O

DDR3L

/DDR3L-RS

SB_DQSP[7:0]

SB_DQSN[7:0]

Data Strobes: SB_DQS[7:0] and its complement signal group

make up a differential strobe pair. The data is captured at the

crossing point of SB_DQS[8:0] and its SB_DQS#[7:0] during

read and write transactions.

I/O

DDR3L/DDR3L-RS

SB_DQ[63:0]

Data Bus: Channel B data signal interface to the SDRAM data

bus.

I/O

DDR3L

/DDR3L-RS

SB_MA[15:0]

Memory Address: These signals are used to provide the

multiplexed row and column address to the SDRAM.

O

DDR3L

/DDR3L-RS

SB_CKP[3:0]
SB_CKN[3:0]

SDRAM Differential Clock: Channel B SDRAM Differential

clock signal pair. The crossing of the positive edge of SB_CKP

and the negative edge of its complement SB_CKN are used to

sample the command and control signals on the SDRAM. Bits

[3:2] used only for 2 DPC system.

O

DDR3L/DDR3L-RS

SB_CKE[3:0]

Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up.
• Power-down SDRAM ranks.
• Place all SDRAM ranks into and out of self-refresh during

STR.

• Bits [3:2] used only for 2 DPC system

O

DDR3L/DDR3L-RS

SB_CS#[3:0]

Chip Select: (1 per rank). These signals are used to select

particular SDRAM components during the active state. There is

one Chip Select for each SDRAM rank. Bits [3:2] are used only

for 2 DPC system.

O

DDR3L/DDR3L-RS

SB_ODT[3:0]

On Die Termination: Active Termination Control. Signals [3:2]

are used only for 2 DPC system.

O

DDR3L/DDR3L-RS

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 328901-007

85