Intel C2550 FH8065401488912 Ficha De Dados
Códigos do produto
FH8065401488912
Volume 2—System Agent and Root Complex—C2000 Product Family
Global Error Reporting
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
76
Order Number: 330061-002US
4.7.3.3
Machine Check Global Control MSRs
These machine check architecture MSRs and bit fields are defined in Section 15.3.1 of
the Intel
®
64 and IA-32 Architectures Software Developer’s Manual. Brief SoC-specific
descriptions follow.
4.7.3.3.1
Machine Check Global Capabilities Register (MSR 179h)
IA32_MCG_CAP
A read-only, 64-bit MSR determines the capabilities of the machine check architecture
of the SoC:
• Bits [63:25] = Reserved.
• Bit 24 = MCG_SER_P - Software Error Recovery Support Present flag. This bit is 0
• Bit 24 = MCG_SER_P - Software Error Recovery Support Present flag. This bit is 0
for the SoC indicating software error recovery is not supported, and
MSR_MCG_CONTAIN (MSR 178h) is not available and should not be accessed.
• Bit [23:16] (8 bits) = MCG_EXT_CNT - Number of Extended Machine Check State
registers. The SoC does not have any MCA Extended Machine Check State
registers. See bit 9 of this register.
• Bits [15:12] = Reserved.
• Bit 11 = MCG_TES_P - Threshold-Based Error Status Present Flag. This bit is 1 for
• Bit 11 = MCG_TES_P - Threshold-Based Error Status Present Flag. This bit is 1 for
the SoC indicating that it provides threshold-based error status in bits [56:53] of
the IA32_MCi_STATUS register. This error-status feature is also called the
yellow/green health reporting.
• Bit 10 = MCG_CMCI_P - Corrected Machine Check (Interrupt) Error
Counting/Signaling Extension Present Flag. This bit is 0 for the SoC indicating it
does not support an extended state nor the associated MSRs necessary to support
the reporting of an interrupt on a corrected error event and/or the threshold
counting of corrected errors.
• Bit 9 = MCG_EXT_P - Extended MSRs Present flag. This bit is 0 for the SoC
indicating that it does not have any MCA Extended Machine Check State registers
which, if they existed, would start at MSR address 180h.
• Bit 8 = MCG_CTL_P - Control MSR Present flag. This bit is 0 for the SoC indicating
the SoC does not have the IA32_MCG_CTL register defined as MSR 17Bh by MCA.
• Bit [7:0] (8 bits) = Count field. Indicates the number of hardware unit
error-reporting banks available in a particular processor implementation. This field
is 6 for the SoC indicating it has six error-reporting banks (0, 1, 2, 3, 4, and 5). In
this document, the letter “i” in a register name represents the bank number of the
MSR. The First Error-Reporting register, IA32_MC0_CTL (bank 0) always starts at
MSR address 400h.