Intel C2518 FH8065501516710 Ficha De Dados
Códigos do produto
FH8065501516710
Volume 2—SoC Reset and Power Supply Sequences—C2000 Product Family
Power Up from G3 State (Mechanical Off)
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
132
Order Number: 330061-002US
See
begins with VDDQ:
1. VDDQ (VDDQA/VDDQB)
— Using VDDQA (Channel 0) and VDDQB (Channel 1) instead of a single VDDQ
voltage source is based on the DDR3 memory component topology of the
platform board.
— Using VDDQA and VDDQB instead of a single VDDQ is based on the DIMM
topology. When the DIMMs are on either side of the SoC, VDDQA and VDDQB
are used for Channel 0 and Channel 1 respectively.
— When VDDQ is valid, the platform asserts the DDR3_0_DRAM_PWROK and
DDR3_1_DRAM_PWROK. The SoC receivers for these signals are powered by
VDDQ.
— The SoC is now in the S3 state. Because the SoC does not support S3, the SoC
does not remain in S3.
— When the SoC is ready to exit the S3 state and advance to the S0 state, it
deasserts the output signals PMU_SLP_S3_B and PMU_SLP_DDRVTT_B. The
platform board design may use the PMU_SLP_DDRVTT_B signal to provide
power to the SDRAM components.
2. This step is optional: Wait for PMU_SLP_S3_B and PMU_SLP_DDRVTT_B output
signals to de-assert.
3. VNN and VCC may begin to ramp-up together.
4. Once VNN and VCC voltages are valid and stable at the SoC pins, VCCSRAM may
4. Once VNN and VCC voltages are valid and stable at the SoC pins, VCCSRAM may
begin to ramp-up at the SoC pins no later than 5 ms. Designers should make this
delay as short as possible.
5. As VCC begins to ramp-up, V1P35S may begin to ramp-up.
6. Once VNN voltage is valid and stable, V1P0S may begin to ramp-up.
7. Once V1P0S begins to ramp-up, V1P8S may begin to ramp-up.
8. VNN, VCC, VCCSRAM, V1P35S, V1P0S, and V1P8S are valid and stable.
9. V3P3S may begin to ramp-up.
6. Once VNN voltage is valid and stable, V1P0S may begin to ramp-up.
7. Once V1P0S begins to ramp-up, V1P8S may begin to ramp-up.
8. VNN, VCC, VCCSRAM, V1P35S, V1P0S, and V1P8S are valid and stable.
9. V3P3S may begin to ramp-up.
See
and
. Once the platform board has all of the DDR3 and core
power well voltage supplies at their valid voltages, and all of the reference clocks are
stable at the SoC input pins, it asserts the COREPWROK signal to the SoC. At the same
time, the platform also asserts the DDR3_0_VCCA_PWROK and
DDR3_1_VCCA_PWROK SoC input signals.
Some of the pin-based straps (hard straps) values are sampled by the SoC when the
platform board asserts the COREPWROK signal to the SoC. These hard strap values
must be valid for at least 400 ns after the COREPWROK signal is asserted. Hard straps
are described in
.
The SoC then deasserts SUS_STAT_B and platform reset (PMU_PLTRST_B).
The platform board and the SoC are now ready to begin functioning in the S0 state. The
SoC internal reset for the core CPU used for the BIOS is completed, and the BIOS
instruction fetching begins from the Flash memory. This core reset is also used for the
SoC output signal, CPU_RESET_B, which the platform board provides to the In-Target
Probe (ITP) connector if part of the board design. It is used only for debug purposes.