Intel C2518 FH8065501516710 Ficha De Dados
Códigos do produto
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 3 of 3
Order Number: 330061-002US
595
Volume 3—Signal Names and Descriptions—C2000 Product Family
GbE, SMBus, and NC-SI Signals
GBE_SDP0_1/
GPIO_SUS18/
NCSI_ARB_IN
I/O
CMOS_V3P3
1
20K, PU
V3P3A
GbE Port 0 SW Defined Pin1:
The SDP pins are reserved
pins that are software
programmable write/read
input/output capability. These
default to inputs upon power-
up, but may have their
direction and output values
defined in the EEPROM. The
SDP bits may be mapped to
the General Purpose Interrupt
bits when configured as
inputs. The SDP0_1 pin can
be used as a watchdog output
indication. The SDP0_1 pin
can be used as a strapping
option to disable PCIe*
Function 0. In this case it is
latched at the rising edge of
PE_RST# or In-Band PCIe
Reset. If GBE_SDP0_1 the
interface is not used, the
signal can be used as GPIO
SUS Port 18. If none of the
above functions are used, the
signal can be used as
NCSI_ARB_IN Arbitration
Input.
GBE_LED0/GPIO_SUS19
O
CMOS_V3P3
1
V3P3A
GBE_LED[3:0] Programming:
0000: Port 0 link up
0001: Port 1 link up
0010: Port 2 link up
0011: Port 3 link up
0100: Port 0 activity
0101: Port 1 activity
0110: Port 2 activity
0111: Port 3 activity
1000: Ports 0-3 “link up”
1001: Ports 0-1 “link up”
1010: Ports 0-3 activity
1011: Ports 0-1 activity
If the GBE_LED[3:0] interface
is not used, the signals can be
used as GPIO SUS Port
[22:19].
GBE_LED1/GPIO_SUS20
O
CMOS_V3P3
1
V3P3A
GBE_LED2/GPIO_SUS21
O
CMOS_V3P3
1
V3P3A
GBE_LED3/GPIO_SUS22
O
CMOS_V3P3
1
V3P3A
NCSI_RXD1/
GPIO_SUS23
O
CMOS_V3P3
1
V3P3A
NC-SI Receive Data 1. Data
signal to the Manageability
Controller (MC).
Note:
NCSI_RXD1 is also a
sampled pin strap
that defines whether
or not the GBE needs
power when the
system is in S5 state.
Settings in the
EEPROM will either
enable or disable the
WOL feature.
Different than
previous generations
of WOL
implementations, the
driver has no control
of this behavior. Refer
Table 31-12. GbE, SMBus, and NC-SI Signals (Sheet 3 of 5)
Signal Name
I/O
Type
I/O Buffer
Type
Ball
Count
Internal
Resistor
PU/PD
External
Resistor
PU/PD
Power
Rail
Description